Non-imprinting memory with high speed erase

ABSTRACT

A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state. A state machine tracks polarity state of the first true/complement data so as to control whether a same polarity or opposite polarity state read operation is performed by the read/write circuit.

PRIORITY CLAIM

This Application claims the benefit of U.S. Provisional Application Patent No. 60/751,263, filed Dec. 16, 2005, the disclosure of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to memories and, in particular, to memories which are non-imprinting and may be reliably and quickly erased.

There are known in the art a number of devices which include a memory for storing information. In some applications of such devices, such as where the device or system requires the storage of information comprising secret, confidential and/or sensitive data, including data such as cryptographic keys, algorithms or identity information. It is a critical system requirement with respect to such device applications to protect the stored information from improper or unauthorized access.

Many of these devices include a functionality for actively detecting an impending attack against the device (such as might occur when an unauthorized attempt is being made to gain access to the information stored in the memory). In response to the detection of such an attack, it is imperative that all secret, confidential and/or sensitive data stored in the memory be erased. In order to minimize, if not eliminate, the risk of access being gained to this information, the erasure of memory contents must be quickly and reliably accomplished by the device itself. The functionality necessary to achieve these goals can be costly and complex.

Many memory cell designs and technologies such as conventional static random access memory (SRAM) all share a common susceptibility to “data imprinting” which refers to a property of the memory to effectuate long term storage of data. In the case of SRAM implementations, the mechanisms for this relate to stresses placed on the gate oxide of a memory cell transistor during operation. These stresses arise as a result of the presence of a constant bias voltage on the memory cell over an extended period coupled with the cell being configured to store data of a certain logical value. This stress can lead to gate oxide charge accumulation which over time can progress to such a degree that it influences the power up state of the memory cell or leave sufficient data remnants which can be passively detected through advanced spectrographic analysis. Thus, the data, which was stored, is said to have left a permanent imprint through the stress induced oxide charge accumulation, and this imprint can be detected, and thus the logic state of the previously stored data identified, for a period of time long after power has been removed from the memory and/or the data has been purposefully erased. A number of active and passive methods are known in the art for discovering the state of an imprinted memory cell. To the extent that the memory cell stored secret, confidential and/or sensitive information, the imprinting would defeat any security actions to erase the cell which were taken in response to a detected impending attack against the device. This, of course, jeopardizes consumer trust in the device and can result in severe damages, which threaten electronic banking systems, facilitate identity theft, defeat access control systems or even more serious issues pertaining to national security.

Presently, the problem of imprinting is addressed by having the host central processing unit (CPU) alter or move data such that the secret, confidential and/or sensitive information does not remain in one memory location for a long enough period of time to imprint. However, designers and manufacturers of these devices or systems may choose not to implement this solution not only due to cost constraints, but also because the actions taken to move the data raise reliability issues (i.e., can the correct state and location of the data be tracked accurately and thus known) and because the read/write operations required for this solution require the consumption of significant amounts of power (which is unacceptable in power sensitive devices). Additionally, attack windows, although narrow, are nonetheless present and can be exploited to gain access to the secret, confidential and/or sensitive information.

As discussed above, in response to a detected impending attack against the device actions are taken by the device to erase all secret, confidential and/or sensitive data stored in the memory. There are problems, however, with the methods by which data is erased. One commonly used technique removes power from the memory and pulls supply voltage to a negative potential. Another technique causes the host CPU for the device to wake up in response to the detected threat and sequentially write to each memory location and thus overwrite the previously stored secret, confidential and/or sensitive data. Unfortunately, as is known in the art, each of these techniques can be relatively easily defeated and thus give a thief an opportunity to obtain access to the data.

In summary, at least two problems exist with conventional memory configurations. First, windows exist which provide sufficient time for data imprinting to take place. Second, the memories can not be reliably and quickly erased. There would be an advantage if means were provided for reliably and quickly erasing all or part of a non-imprinting memory which stores secret, confidential and/or sensitive information.

BRIEF SUMMARY OF THE INVENTION

In accordance with this specific embodiment of the invention, a random access memory cell comprises a master cell storing true/complement data and a slave cell storing true/complement data. A circuit interconnects the master cell and slave cell. This circuit receives first and second non-overlapping clock signals and is operable responsive to a change in state of the first clock signal to copy the true/complement data from the master cell for same polarity storage in the slave cell, and is further operable responsive to a change in state of the second clock signal to copy the true/complement data from the slave cell for opposite polarity storage in the master cell.

In accordance with another embodiment, a memory cell comprises a master cell storing first data and a slave cell storing second data. A first circuit is associated with the slave cell and operates responsive to a first control signal to copy first data from the master cell into the slave cell with same state to be the second data. A second circuit is associated with the master cell and operates response to a second control signal to copy second data from the slave cell into the master cell with complementary state to be the first data.

In accordance with yet another embodiment, a device comprises a memory cell including a master cell storing first data, a slave cell storing second data, a first circuit associated with the slave cell and operable responsive to a first control signal to copy first data from the master cell into the slave cell with same state to be the second data, and a second circuit associated with the master cell and operable response to a second control signal to copy second data from the slave cell into the master cell with complementary state to be the first data. The device further comprises a state machine which is operable to track over time a polarity of the first data which is stored in the master cell of the memory cell.

In another embodiment, a circuit comprises a master memory cell storing first true/complement data and a slave memory cell storing second true/complement data. A first circuit is associated with the slave cell and operates responsive to a first clock signal to copy first true/complement data from the master memory cell into the slave memory cell with same state to be the second true/complement data. A second circuit is associated with the master memory cell and operates response to a second clock signal, which is a complement of the first clock signal, to copy second true/complement data from the slave memory cell into the master memory cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master memory cell in either same polarity or opposite polarity state. A state machine tracks polarity state of the first true/complement data so as to control whether a same polarity or opposite polarity state read operation is performed by the read/write circuit.

The above summary of the invention is not intended to represent each embodiment or every aspect of the present invention. In principle, an embodiment of the present invention concerns a memory device wherein no single data storage entity is capable of leaving any traceable remnants of previously stored data. A particular technique for accomplishing this goal is through the constant (or timely) exchange of data states between primary and secondary elements which comprise each date storage entity. The memory device is preferably formed of a plural number of data storage entities as described above, perhaps organized in the form of an array. In accordance with an aspect of the invention, the plurality of data storage entities, of limitless size, can be simultaneously erased.

The data storage entity may, in one implementation, comprise a transistor-based memory circuit. It will be understood, however, that the invention applies to any memory technology subject to imprinting concerns (for example, ferro-magnetic memory devices, quantum memory devices, organic memory devices, biologic memory devices, and the like).

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the method and apparatus of the present invention may be obtained by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:

FIG. 1 is a schematic diagram of a circuit for implementing a non-imprinting memory cell with high speed erase in accordance with an embodiment of the invention; and

FIG. 2 is a block diagram of a device within which the non-imprinting memory cell with high speed erase (signal R) of FIG. 1 may be advantageously used.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made to FIG. 1 wherein there is shown a schematic diagram of a circuit for implementing a non-imprinting memory cell with high speed erase in accordance with an embodiment of the invention. The memory cell 10 includes a master memory cell 12 and a slave memory cell 14 which are interconnected with each other. It will be recognized and understood that the cell 10 can comprise just a single cell (for storing a single bit) of a multi-bit memory of any suitable arrangement. Although the memory cell 10 is illustrated for exemplary convenience as a transistor-based memory device, it will be understood that the memory cell 10 can comprise any type of memory device which is subject to concerns over imprinting. For example, the memory cell may alternatively comprise a ferro-magnetic-based device, a quantum-based device, a organic-based device or a biologic-based device. The master and slave cells 12 and 14 are also illustrated for exemplary convenience as a transistor-based devices, but it will be understood that the cells 12 and 14 will be of the same type (ferro-, quantum-, organic- and biologic-) as the cell 10 to which they pertain.

The master cell 12, in the exemplary transistor-based design, includes first and second inverters 16 and 18, respectively, which are head-to-tail coupled to form a first latch 20. More specifically, the output of inverter 16 at node Q is coupled to the input of inverter 18, while the output of inverter 18 at node QB is coupled to the input of inverter 16. In this way, the first latch 20 stores data at node Q, while its complement is stored on node QB.

Similarly, the slave cell 14, in the exemplary transistor-based design, includes first and second inverters 22 and 24, respectively, which are head-to-tail coupled to form a second latch 26. More specifically, the output of inverter 22 at node S is coupled to the input of inverter 24, while the output of inverter 24 at node SB is coupled to the input of inverter 16. In this way, the second latch 26 stores data at node S, while its complement is stored on node SB.

Node QB in the master cell 12 is coupled to ground through drain-source series connected nMOS 30 and nMOS 32. A gate of nMOS 30 is coupled to node SB of the slave cell 14. Node Q in the master cell 12 is coupled to ground through drain-source series connected nMOS 34 and nMOS 36. A gate of NMOS 34 is coupled to node S of the slave cell 14. The gates of nMOS 32 and nMOS 36 both receive a clock signal ph2.

Node SB in the slave cell 14 is coupled to ground through drain-source series connected nMOS 38 and nMOS 40. A gate of nMOS 38 is coupled to node Q of the master cell 14. Node S in the slave cell 14 is coupled to ground through drain-source series connected nMOS 42 and nMOS 44. A gate of nMOS 42 is coupled to node QB of the master cell 12. The gates of nMOS 40 and nMOS 44 both receive a clock signal ph1.

The clock signals ph1 and ph2 are non-overlapping, and are generated by a state machine (see, FIG. 2) using conventional techniques.

Node Q in the master cell 12 is further coupled to ground through the drain-source circuit of nMOS 50. Node SB in the slave cell 14 is further coupled to ground through the drain-source circuit of nMOS 52. The gate terminals of nMOS 50 and nMOS 52 both receive a reset signal R. Upon a power-up event, the reset signal R is pulsed high (perhaps by the state machine or other control device such as a central processing unit or a power on reset circuit). With gates of nMOS 50 and NMOS 52 both at logic high, these transistors are turned on and nodes Q and SB are driven to ground voltage. Through operation of the first latch 20, complement node QB is accordingly set to logic high. Similarly, through the operation of the second latch 26, complement node S is accordingly set to logic high. In this way, at reset, the master and slave cells 12 and 14, respectively, of the memory cell 10 are set to a known initial state (for example, low and high, respectively).

The reset signal R is also activated by a tamper detect functionality (see, FIG. 2) which actively operates to detect an impending attack against a device which contains the memory cell 10 (such as might occur when an unauthorized attempt is being made to gain access to the information stored in the memory cell). In response thereto, the tamper detect functionality will pulse the reset signal R high. This turns on nMOS 50 and nMOS 52 and drives nodes Q and SB to ground voltage thus setting the memory cell 10 back to its known initial state (low and high). This clearing of the memory cell is accomplished both reliably and very quickly to thus thwart any attempt by the tamperer to gain access to secret, confidential and/or sensitive data which was stored in the memory cell 10. Where plural cells 10 are present in a memory, the reset signal R is simultaneously applied to all of those cells so as to effectuate a simultaneous erase of those cells. Advantageously, the reset signal R response circuit configuration with nMOS transistors 50 and 52 as shown supports substantially simultaneous reset of a plurality of cells 10 of essentially limitless size (i.e., in number).

The memory cell 10 is of no value unless it can be read from and written to. A read/write circuit 60 is accordingly provided to support read/write operations. The memory cell 10 is connected to a pair of complementary data (or bit) lines (or pins) labeled as nodes D and DB, respectively. An nMOS 62 is drain-source circuit connected between node D and node Q, while an nMOS 64 is drain-source circuit connected between node DB and node QB. The gates of nMOS 62 and nMOS 64 receive a true control signal ADDRT whose operation will be explained later. Conversely, an nMOS 66 is drain-source circuit connected between node D and node QB, while an nMOS 68 is drain-source circuit connected between node DB and node Q. The gates of nMOS 66 and nMOS 68 receive a complement control signal ADDRB whose operation will be explained later. The ADDRT and ADDRB signals are generated, responsive to an address decode for example which selects the memory cell 10, by a state machine (see, FIG. 2) using conventional techniques and in accordance with the conditions described herein.

To write into the memory cell 10, the desired data and its complement are applied to nodes D and DB. If one wishes to store non-inverted (i.e., true) data in the memory cell 10, then the ADDRT signal (true) is forced to logic high which turns on nMOS transistors 62 and 64 to set node Q to the logic state present at node D and node QB to the logic state present at node DB. Conversely, if one wishes to store inverted (i.e., false or complement) data in the memory cell 10, then the ADDRB signal (false) is forced to logic high which turns on nMOS transistors 66 and 68 to set node Q to the logic state present at node DB and node QB to the logic state present at node D. It will be noted, for either case, that the logic values loaded during the write operation into nodes Q and QB will also be applied to the gates of nMOS transistors 38 and 42, respectively, in the slave cell 14.

To read from the memory cell 10, and assuming one wishes to recover non-inverted (i.e., true) data, then the ADDRT signal (true) is forced to logic high which turns on nMOS transistors 62 and 64 to set node D to the logic state stored at node Q of the latch 20 and node DB to the logic state stored at node QB of the latch 20. Conversely, if one wishes to recover inverted (i.e., false or complement) data as read from the memory cell 10, then the ADDRB signal (false) is forced to logic high which turns on nMOS transistors 66 and 68 to set node D to logic state stored at node QB of the latch 20 and node DB to the logic state stored at node Q of the latch 20. The reason why support for reading both true and complement polarities with respect to the stored data must be supported will become clear with reference to operation of the memory cell to preclude imprinting.

The memory cell 10 addresses the imprinting issue by constantly inverting the data which is stored in the memory cell. This is accomplished through the interconnection of the master cell 12 and slave cell 14 as discussed above and the cooperative operation of the master and slave cells under the control of the clock signals ph1 and ph2. As mentioned previously, the clock signals ph1 and ph2 are non-overlapping inversions of each other. When the clock signal ph1 is logic high, nMOS 40 and nMOS 44 are turned on and the data stored in the master cell 12 is copied to the slave cell 14. This occurs through the operation of nMOS 38 and nMOS 42. Assuming ph1 is logic high, if Q is also logic high (and thus QB is logic low), nMOS 38 (whose gate is coupled to node Q) is turned on along with nMOS 40 to drive node SB of the slave cell 14 to ground. Operation of the latch 26 then sets node S to logic high. Thus, slave cell 14 is set identically to master cell 12. When the clock signal ph1 then goes to logic low, clock signal ph2 will become logic high at some time later, when this happens nMOS 32 and nMOS 36 are turned on and the data stored in the slave cell 14 is copied, with an inversion of state (i.e., a polarity change), to the master cell 12. This occurs through the operation of nMOS 30 and nMOS 34. Assuming ph2 is logic high, if S is also logic high (and thus SB is logic low), nMOS 34 (whose gate is coupled to node S) is turned on along with nMOS 36 to drive node Q of the master cell 12 to ground. Note here that this is exactly the opposite logic state for node Q from the starting point in time when ph1 first went to logic high. Operation of the latch 20 then sets node QB to logic high. Thus, master cell 12 is set complementarily to slave cell 14.

Since ph1 and ph2 are complementary clock signals, this copying, shuffling and inversion with respect to the stored data state among and between the master cell 12 and slave cell 14 of the memory 10 continues, back and forth, for so long as the clock signals continue to run. Importantly, the shuffling and inversion of the data prevents a constant voltage from being applied to the gate oxide of any one or more of the data storing transistors of the memory cell 10 for an excess amount of time, thus preventing oxide charge accumulation and the resulting imprinting problem from occurring. When a read or write operation needs to be performed with respect to the memory 10, the clocks are either stopped or ignored for the duration of the read/write. Thereafter, the clocks continue to drive the constantly inverting operation.

With each completed cycle of the clocks ph1 and ph2, the logic state of the data stored in the master cell 12 inverts. It is thus critical, if one wants to be able to properly read out the stored data (i.e., in the correct original state), to keep track of true versus complement state (or polarity) of the stored data as the clocks ph1 and ph2 run. The state machine (see, FIG. 2) referenced above is charged with the responsibility of tracking the polarity of the data stored in the master cell 12. This is where the ADDRT and ADDRB control signals, as well as the nMOS transistors 62-68 come back into play. By tracking data polarity, the state machine can determine which of the control signals ADDRT or ADDRB to assert when a read or write to the memory 10 needs to occur (and clock operation is paused or ignored).

Consider for a moment the exemplary operation described above where one cycle of the ph1 and ph2 clocks was completed. After that one cycle, the master cell 12 would be storing the complement of the originally stored data. Assuming a read of the data stored in the master cell 12 needed to occur at this time, the state machine would assert the ADDRB control signal and activate nMOS transistors 66 and 68. The reason for this is that the drain-source connections of nMOS transistors 66 and 68 are configured to place data from the complement node QB of the latch 20 on the true data node D, while placing the data from the true node Q of the latch 20 on the complement data node DB. In this way, the read/write circuit 60 inverts the stored data in the master cell 12 and thus corrects for the data inversion implemented through the completed first cycle of the clocks ph1 and ph2.

Now, if the clocks were to proceed for another cycle, it would be recognized that the copying, shuffling and inversion operation, in a manner similar to that described above, would return the master cell 12 back to its initial data state. Assuming a read of the data stored in the master cell 12 needed to occur at this time, the state machine would assert the ADDRT control signal and activate nMOS transistors 62 and 64. The reason for this is that the drain-source connections of nMOS transistors 62 and 64 are configured to place data from the true node Q of the latch 20 on the true data node D, while placing the data from the complement node QB of the latch 20 on the complement data node DB. In this way, the read/write circuit 60 does not invert the stored data in the master cell 12.

Given the foregoing, it will be noted that after a certain initial data polarity is established in the master cell 12 (for example, when a write is performed), the state machine need only keep track of the number of ph1/ph2 clock cycles which are completed thereafter. With that knowledge, the state machine can properly select the ADDRT or ADDRB control signal to assert when a read from the memory 10 needs to occur. For example, as shown above, for any odd numbered completed ph1/ph2 clock cycles, the ADDRB control signal should be asserted during read (since an inversion of the original data has occurred), while for any even numbered completed ph1/ph2 clock cycles, the ADDRT control signal should be asserted during read (since the inversion of the original data has been corrected). The state machine could use a simple single bit flag to track this data polarity issue. Thus, for each completed ph1/ph2 clock cycle, the state of the flag is changed between logic high and logic low, with the current flag logic state then used to select which one of the ADDRT or ADDRB control signal to assert when the clocks are subsequently stopped to allow for a read operation to be performed.

FIG. 1 illustrates the circuit for just a single bit (or cell 10) of what could be a much larger multi-bit memory (configured in a register or array format or the like as desired). Each bit of the memory would include both a master cell 12 and a slave cell 14. The memory cell 10 (bit) would be non-imprinting (through operation of the copying, shuffling and inversion operation described above) and support a quick and reliable data erase/reset (through use of the reset signal R). The state machine, which could be integrated with or separately from the memory, controls operation by performing the following operations: a) keeping track of data polarity and thus determining which one of the ADDRT or ADDRB control signals to assert, b) asserting ph1 and ph2 (two phases of a non-overlapping clock) to facilitate the bit copying, shuffling and inversion operation, and c) halting running of the ph1 and ph2 clock signals, or causing the clocks to be ignored, in the event a memory access (read or write) operation needs to be performed.

Although the transistor-based exemplary design is illustrated using n-channel transistors, it will be understood that an equivalent design could alternatively use p-channel devices, or a combination of n-channel and p-channel devices. The use of FET-type devices is similarly only exemplary, and an equivalent design could alternatively use bi-polar devices.

Reference is now made to FIG. 2 wherein there is shown a block diagram of a device 100 within which the non-imprinting memory cell 10 with high speed erase of FIG. 1 may be advantageously used. The device 100 includes a constantly complementing memory circuit 102 comprised of a plurality of memory cells 10 which may be arranged in any selected architecture including a linear register and an array. The memory circuit 102 includes all necessary addressing circuitry to control selection of individual ones and/or groups of individual ones of the memory cells 10. This addressing circuitry may utilize address decoder and driver circuits which are well known to those skilled in the art. Integrating such circuits to activate memory cells 10 for read and write operations is well within the capabilities of those skilled in the art.

The device 100 further includes a memory controller circuit 104. The circuit 104 may comprise, for example, any suitable memory controller circuit including integrated controller circuits available from Maxim Integrated Products. Alternatively, the circuit 104 can comprise any suitable microcontroller, microprocessor, central processing unit or other programmable control device known in the art which can operation to control access to the memory 102.

The circuit 104 includes a tamper detection circuit 106. This circuit 106 can be implemented in any selected fashion known to those skilled in the art, including having the circuit as an embedded functionality within the memory controller integrated circuit chip. Generally speaking, the circuit 106 functions to actively detect an impending attack against the device 100 (such as might occur when an unauthorized attempt is being made to gain access to the information stored in the memory 102). In response thereto, the circuit 106 issues a reset signal R which is applied to each memory cell 10 within the memory 102 to set the memory cells 10 back to a known initial state. This clearing of the memory cells is accomplished both reliably and very quickly to thus thwart any attempt by the tamperer to gain access to secret, confidential and/or sensitive data which may be stored in the memory cells 10.

The circuit 104 supports an I²C 2-wire serial input/output bus through the SCL and SDA ports. While a 2-wire serial bus comprises a preferred I/O implementation for the device 100, other implementations based on SPI type, three or four wire interfaces have been implemented. It will of course be understood by those skilled in the art that the I/O functionality can take on any one of many available known forms including both serial and parallel configurations.

The circuit 104 includes the clock generating functionality for supplying the controlled ph1 and ph2 clock signals. The circuit further includes functionality for implementing the state machine 108 which is operable in the manner described above to control the copying, shuffling and inversion operation of the memory cells 10 of the constantly complementing memory 102.

Advantageously, the copying, shuffling and inversion operation performed by each of the memory cells 10 addresses the memory imprinting issue without requiring data to be moved around the memory 102. The address location for each piece of data need not change and thus there is no need for a controller or central processing unit to keep track of changing memory locations as with some prior art designs. Additionally, because the copying, shuffling and inversion operation is effectuated through a circuit under the control of a clock signal, significant controller or central processing unit oversight is not required. Still further, the circuit and clock signal design shown in FIG. 1 requires much less power to operate than other prior art imprinting solutions. Yet another advantage of the circuit of FIG. 1 resides in the simplicity of the reset operation where a single reset line can be pulsed to quickly, effectively and reliably cause large numbers of memory cells to be cleared (reset) of data.

Generally speaking, the device 100 within which the non-imprinting memory cell 10 with high speed erase of FIG. 1 can be advantageously used can be: 1) a Secure Transaction Terminal, such as is involved with the exchange of financial information; 2) Software Defined Radio Equipment; 3) Trusted Computing and Public Key Infrastructure Equipment; or 4) Physical Access Control Equipment.

With respect to Secure Transaction Terminals, these devices are also commonly referred to as Point of Sale (POS) terminals (or Credit Card terminals). They are used anywhere credit cards are accepted. By sliding the magnetic strip side of the credit card through a slot, information is read by the terminal and the transaction is performed. With respect to the present invention, a non imprinting memory would provide benefits to this equipment with respect to protecting the confidential information extracted from credit cards. Additionally, the non imprinting memory could also form a part of a credit card itself to store confidential information.

With respect to Software Defined Radio Equipment, this refers to the secure radios often used by the military, police, fire fighters, ambulance, border security, healthcare, transportation. These radios are typically used in environments where secure communications are necessary (i.e., the parties to the communication must be verified and the communications themselves must be protected against eavesdropping). These radios may operate over a special network and require that an authentication key be verified in order for the communication to be established. With respect to the present invention, a non imprinting memory would provide benefits to this equipment with respect to protecting the secret keys or codes needed for authenticating parties to the communications or establishing the communications links.

With respect to Access Control and PKI, these two subjects are closely related within the scope of the present invention. The access control market has traditionally been one of the largest markets for authentication devices. As the needs for increased security have been escalated, this industry is facing the need to make significant upgrades to their equipment through more advanced encryption and authentication techniques. Access control products fall into two arenas: 1) Physical access control relates to allowing access to Facilities such as Buildings, Transportation systems, etc.; and 2) Information access control relates to the access of digital information such as website content, corporate Intranets etc. In each of these cases, there exists a central trusted point which issues, validates and administrates encryption key information. The purpose of this is to provide a trusted source of information which can validate digital signatures to be genuine. The systems that perform this utilize both asymmetrical and symmetrical encryption techniques. However, the most critical part of the process is the generation of asymmetrical public and private key pairs through a process known as RSA. During the key generation process, the user and PKI administrator establish each others identity through a process suitable to both parties. Once this root of trust has been accomplished the PKI cooperates with the users computer, smart card or other suitable digital device to generate and issue a digitally signed certificate based upon the users public and private key pair. The user's private key is never to be provided outside the users control and must assure it remains un-compromised. For if the users private key(s) got out, there identities could be stolen giving the attacker access to all facilities granted by the PKI's certificate. An even more terrifying scenario exists if the PKI's private keys were stolen, as this could result in a wide scale attack on all users who depend upon the PKI's security. Although there are secondary measures which can be employed in order to mitigate this threat (PIN PADS, Biometrics, Compartmentalized System Administration etc.), it is clear that the storage of digital certificates and their associated private keys must be diligently managed and protected. This PKI or central point can take many forms depending upon the size and scope of the information which requires protection and authentication. This can range from governments to private enterprises. The equipment utilized consists of servers equipped with dedicated cryptographic coprocessors, specialized software, highly secure networks and infrastructure interfaces. All of which is stored and administrated in a suitably secure facility. With respect to the present invention, a non imprinting memory would provide benefits to equipment used on both the client and PKI's side of an authentication/access control system and would include any digital device which stores and processes RSA or other asymmetrical encryption algorithms and their associated keys.

Although various embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth herein. 

1. A random access memory cell, comprising: a master cell, coupled within the random access memory cell, that stores a first digital state, corresponding to a bit value, for a first time period; a slave cell, coupled within the random access memory cell, that stores a complement of the first digital state, corresponding to the bit, for the first time period; a state identifier that allows a value of the bit to be identified from the first digital state or the complement of the first digital state; and a circuit coupling the master cell and slave cell that changes the first digital state within the master cell to the complement of the first digital state for a second time period and causes a modification to the state identifier.
 2. The random access memory cell of claim 1 wherein a pre-determined clock cycle is used to define the first and second time periods.
 3. The random access memory cell of claim 1 wherein the master and slave cells each comprise a data latch supporting a true node and a complement node.
 4. The random access memory cell of claim 3 wherein the data latch for each cell comprises a pair of head-to-toe coupled inverter circuits.
 5. The random access memory cell of claim 3 wherein the circuit comprises, associated with each data latch, first and second MOS transistors coupled in series between the true node and a reference voltage, and third and fourth MOS transistors coupled in series between the false node and the reference voltage.
 6. The random access memory cell of claim 5 wherein, for one of the data latches, the second and fourth MOS transistors are gate connected to receive one of the first/second clock signals, and the first and third MOS transistors are gate connected to true/complement nodes of another of the data latches.
 7. The random access memory cell of claim 6 wherein the first and third MOS transistors associated with the slave cell data latch are gate connected to the true/complement nodes of the master cell data latch in same logic state polarity, and wherein the first and third MOS transistors associated with the master cell data latch are gate connected to the true/complement nodes of the slave cell data latch in opposite logic state polarity.
 8. The random access memory cell of claim 1 further including a read/write circuit coupled to the master cell for reading true/complement data from and writing true/complement data to the master cell.
 9. The random access memory cell of claim 8 wherein the read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.
 10. The random access memory cell of claim 1 further comprising a reset circuit operable responsive to a reset signal to set the master cell and slave cell each to a known true/complement data state.
 11. A memory cell, comprising: a master cell storing a first data state, corresponding to a bit value, for a first time period; a slave cell storing a second data state corresponding to the bit value and complimentary of the first data state; a first circuit associated with the slave cell and responsive to a first control signal to copy the first data state from the master cell into the slave cell a second circuit associated with the master cell and responsive to a second control signal to copy the second data state from the slave cell into the master cell and store the second data state within the master cell for a second period of time.
 12. The memory cell of claim 11 wherein the first and second control signals comprise complementary non-overlapping clock signals.
 13. The memory cell of claim 11 further comprising a read/write circuit coupled to the master cell for reading first data from and writing first data to the master cell.
 14. The memory cell of claim 13 wherein the read/write circuit includes circuitry for supporting data read and write operations with respect to the master cell in either true or complement first data state.
 15. A multi-bit memory, comprising: a plurality of memory cells; each memory cell configured to store a single bit value by storing a first state for a first period of time and a second state for a second period of time; and wherein a state identifier is maintained that allows the single bit value to be derived from either the first state or the second state.
 16. The multi-bit memory of claim 15 further comprising a reset circuit for setting a reset state on each memory cell within the plurality of memory cells.
 17. The multi-bit memory of claim 15 wherein at least one clock signal defines a length of the first time period and a length of the second time period.
 18. The multi-bit memory of claim 15 further comprising a read/write circuit that retrieves the single bit value from a first memory cell, within the plurality of memory cells, by reading the first state or the second state and the state identifier.
 19. The multi-bit memory of claim 18 wherein the read/write circuit writes the single bit value to the first memory cell by storing the first state within the first memory cell and setting the state identifier to a first state value.
 20. A device, comprising: a memory cell including a master cell storing first data, a slave cell storing second data, a first circuit associated with the slave cell and operable responsive to a first control signal to copy first data from the master cell into the slave cell with same state to be the second data, and a second circuit associated with the master cell and operable response to a second control signal to copy second data from the slave cell into the master cell with complementary state to be the first data; and a state machine operable to track over time a polarity of the first data which is stored in the master cell of the memory cell.
 21. The device of claim 20 wherein the memory cell further includes a read circuit coupled to the master cell for supporting first data read operations with respect to the master cell in either same polarity or opposite polarity state based on state machine tracking over time of stored first data polarity.
 22. The device of claim 21 wherein the state machine issues a read control command specifying either same polarity of opposite polarity reading of the master cell stored first data in response to tracked first data polarity.
 23. The device of claim 20 wherein the first and second control signals comprise complementary non-overlapping clock signals.
 24. The device of claim 23 wherein the state machine tracks cycles of the clock signals to provide an indication of polarity of the first data which is stored in the master cell.
 25. The device of claim 24 wherein the memory cell further includes a read circuit coupled to the master cell for reading first data from the master cell in either same polarity or opposite polarity state based on state machine indication of polarity tracked through cycles for the clock signals.
 26. The device of claim 20 wherein the device comprises secure transaction terminal.
 27. The device of claim 20 wherein the device comprises software defined radio equipment.
 28. The device of claim 20 wherein the device comprises trusted computing or public key infrastructure equipment.
 29. The device of claim 20 wherein the device comprises physical access control equipment.
 30. A circuit, comprising: a master memory cell storing first true/complement data; a slave memory cell storing second true/complement data; a first circuit associated with the slave cell and operable responsive to a first clock signal to copy first true/complement data from the master memory cell into the slave memory cell with same state to be the second true/complement data; a second circuit associated with the master memory cell and operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave memory cell into the master memory cell with complementary state to be the first true/complement data; a read/write circuit including circuitry for supporting true/complement data read and write operations with respect to the master memory cell in either same polarity or opposite polarity state; and a state machine that tracks polarity state of the first true/complement data so as to control whether a same polarity or opposite polarity state read operation is performed by the read/write circuit.
 31. A method for storing a bit value within a memory cell, the method comprising: storing a first state value, corresponding to the bit value, for a first period of time within the memory cell; setting a state identifier to a first identifier value that associates the first state value with the bit value; storing a second state value, being complimentary to the first state value, for a second period of time within the memory cell; and changing the state identifier to a second identifier value that associates the second state value with the bit value.
 32. The method of claim 31 wherein a transition from the first state value to the second state value within the memory cell is defined by a pre-defined clock cycle.
 33. The method of claim 31 wherein the state identifier is maintained externally from the memory cell.
 34. The method of claim 31 wherein the state identifier is maintained internally within the memory cell.
 35. The method of claim 31 wherein the state identifier is a first binary value associated with the first state value or a second binary value associated with the compliment of the first state value.
 36. The method of claim 31 wherein the memory cell is integrated within a plurality of memory cells maintained within a random access memory device.
 37. The method of claim 36 wherein the plurality of memory cells also includes a state flag that stores the state identifier associated with the memory cell.
 38. The method of claim 37 wherein the state flag, and the state identifier stored therein, identifies a state for a set of memory cells within the plurality of memory cells.
 39. The method of claim 31 wherein the memory cell comprises a master cell and a slave cell that allow the first state value and second state value to be stored within the memory cell.
 40. The method of claim 31 wherein the memory cell comprises a single cell in which the first state value is stored during the first period and second state value is stored during the second period.
 41. The method of claim 40 wherein a state flag is associated with the memory cell and stores the first identifier value and the second identifier value. 